1. Field of the Invention
The present invention relates to a display driver for driving a display apparatus such as a liquid crystal display, etc., and in particular relates to improvement of a display driver constructed in a way to drive the display apparatus by supplying the display apparatus by time sharing with the potential of two reference power sources selected from among a plural number of reference power sources depending on the displayed data.
2. Description of the Related Art
Prior art will be explained below by taking the digital drive source driver of a liquid crystal display apparatus of Thin Film Transistor (hereinafter abbreviated as "TFT") type as an example.
FIG. 1 is a drawing showing a TFT liquid crystal display apparatus 11 and a gate driver integrated circuit (hereinafter abbreviated as "IC") 12 which is a driver thereof, and a source driver IC 13. Each picture element of the TFT liquid crystal display apparatus 11 consists of a TFT (Metal Oxide Semiconductor Field Effect Transistor, hereinafter abbreviated as "MOSFET") 111 and a liquid crystal element 112. The gate driver IC 12 outputs gate drive pulses G1, . . . , GM with phases shifted one after another. On the other hand, the source driver IC 13 (8-gradation display) outputs one selected potential or two selected potentials by time sharing from among the reference power sources V0, V4 and V7 (supplied from outside through terminals T0, T4 and T7 respectively) according to the display data D0, D1 and D2 input from a display controller (not shown) at the output terminals OT1, . . . , OTN.
FIG. 2 shows the internal construction of the source driver IC 13. The circuit of FIG. 2 represents a circuit corresponding to one of the output terminals OT1, . . . , OTN, and N similar circuits are provided in parallel inside the source driver IC 13.
D0, D1, D2 represent display data DM0, DM1, DM2 represent data memory circuits which fetch and store display data at the timing of clock signal SRi (i=1, . . . N). DL0, DL1, DL2 represent latch circuits which latch the output of the data memory circuits DM0, DM1, DM2, respectively, at the timing of clock signals LS, V0, V4, V7 represent reference power sources. L0, L4, L7 represent supply lines of reference power sources V0, V4, V7 respectively, AS0, AS4, AS7 represent analogue switches installed on the respective power supply lines. L0, L4, L7, DK represents a decoder circuit which outputs CAS0, CAS4, CAS7 controlling opening/closing of the analogue switches AS0, AS4, AS7 based on the output of display latch circuits DL0, DL1, DL2 and a clock signal CK (35 MHz) a Oi is an output. The clock signal SRi is a timing signal with a phase shifted one after another output from the shift register incorporated in the source driver IC 13.
Table 1 indicates the correspondence between the input display data D2, D1, D0 and the output signals CAS0, CAS4, CAS7 of the decoder circuit DK.
TABLE 1 ______________________________________ D2 D1 D0 CAS0 CAS4 CAS7 ______________________________________ 0 0 0 1 0 0 1 3t 3t 0 1 0 2t 2t 0 1 1 1t 1t 1 0 0 1 1 0 1 3t 3t 1 1 0 2t 2t 1 1 1 1 ______________________________________
The blank parts in the table are all "0".
FIG. 3 shows the waveform of the clock signal CK and of the decoder circuit output signals 1t-3t and 1 given in Table 1.
FIG. 4 shows an example of construction of the decoder circuit DK. This circuit is composed of 2-step D type flip-flops DF1, DF2 constituting the dividing circuit of the clock signal CK and a logical gate LG which generates and outputs analogue switch control signals CAS0, CAS4, CAS7 given in Table 1 based on the output of the flip-flops and the display data.
Moreover, FIG. 5 shows an example of construction of analogue switches AS0, etc. In the example of FIG. 5, each switch includes a CMOS transfer gate, but it may also include a transfer gate composed only of a MOS transistor of one channel which does not produce any voltage drop of threshold value. For example, the analogue switches AS0, AS4 may be constructed respectively with a MOS transistor of N channel only. Moreover, the analogue switches AS4, AS7 may be constructed respectively with a MOS transistor of P channel only by reversing the output of the decoder circuit.
Next, the operation of the circuit of FIG. 2 will be described based on the timing chart of FIG. 6.
As shown in FIG. 6, when the clock signal SRi controlling the data memory circuits DM0, DM1, DM2 is at the high level, the 3-bit display data D0, D1, D2 are taken into the data memory circuits concerned, and then they are output directly from the output Q and led to the display latch circuits DL0, DL1, DL2. When the clock signal SRi has fallen from high level to low level, the data memory circuits DM0-DM2 maintain the values of D0 to D2 and, during the period when the clock signal SRi remains at the low level, the output Q of the data memory circuits DM0-DM2 does not change even if there is some change in the input display data D0 to D2. Next, when the clock signal LS controlling the display latch circuits DL0-DL2 is at the high level, the output Q of the data memory circuits DM0-DM2 is led directly to the output Q of the display latch circuits DL0-DL2. When the signal LS has fallen from high level to low level, the data of the output Q of the data memory circuits DMO-DM2 at that point in time is retained in the output Q of the display latch circuits DL0-DL2. Moreover, during the period when the signal LS is at the low level, the output Q of the display latch circuits DL0-DL2 does not change even if there is some change in the output Q of the data memory circuits DM0-DM2. The output Q of the display latch circuits DL0-DL2 is led to the input of the decoder circuit DK. The decoder circuit DK outputs analogue switch control signals CAS0, CAS4, CAS7 as shown in Table 1. For example, when the display data D2, D1, D0 are "000", the decoder circuit DK outputs a signal with which only the analogue switch AS0 is turned on. Thereby, the potential of the reference power source V0 is output to the output Oi and then fed to the liquid crystal display apparatus. Moreover, when the display data D2, D1, D0 are "011", the decoder circuit DK outputs a signal with which the analogue switch AS0 is turned on for a quarter period, the analogue switch AS4 is turned on for the following 3 quarter periods by turning off the analogue switch AS0, and these operations are alternately repeated. As a result, the potential of the reference power source V0 and the potential of the reference power source V4 are alternately output to the output Oi in the proportion of time of 1:3 and are fed to the TFT liquid crystal display apparatus 11.
FIG. 2 shows one output unit of a drive circuit which feeds 3 levels of reference supply voltage as display signals to the TFT liquid crystal display apparatus 11. For example, he number of output terminals of the source driver IC 13 of a TFT liquid crystal display apparatus 11 is 120 to 240 or so, and this number is expected to further increase in the future. Moreover, considering the purpose of the use of a digital drive source driver, a liquid crystal display of office automation (hereinafter abbreviated as "OA") equipment can be imagined naturally, and it is expected that a rectangular display (e.g., window display) will be more commonly used for the display image of such a liquid crystal display. Considering the output value of horizontal period of the digital drive source driver driving the liquid crystal display in the case of such a rectangular display, for example, in the case where the outputs of No. 1 output terminal OT1 to No. n output terminal OTn are a background picture with a voltage level of V6, the outputs of No. n+1 output terminal OTn+1 to No. n+100 output terminal OTn+100 are a window display with a voltage level of V1 and that the output of No. n+101 output terminal OTn+101 to final output terminal OTN displays a background picture with a voltage level of V6, for example, the levels of the reference power source V7 and the reference power source V4 in a period 1 produce a voltage drop because the current i flows from the reference power sources to the load as shown in FIGS. 7 and 8. Next, as shown in FIGS. 7 and 9, the current i flows into the load in a period 2 continuously from the period 1, and the level of the reference power source V7 in the period 2 produces a further voltage drop. On the other hand, the electric charge which has flowed from the reference power source V4 to the load flows next to the reference power source V0, causing a voltage build-up in the level of the reference power source V0. Lastly, as shown in FIGS. 7 and 10, in a period 3, the electric charge which has flowed from the reference power source V7 to the load flows to the reference power source V4 while the electric charge which has flowed from the reference power source V4 to the load flows to the reference power source V0, and this causes a voltage build-up in the levels of the reference power source V4 and the reference power source V0.
Accordingly, when an intermediate voltage is produced by turning on/off between two reference power sources, there is good reason to believe that voltage fluctuations in the reference power sources themselves make it difficult to supply a stable voltage to the display apparatus, leading to a drop of display definition, if the reference power sources repeats voltage-drop and voltage build-up as the reference power source V4 does.